Semiconductor memory device

ABSTRACT

A semiconductor memory device includes a first first-type well including a first cell array for storing a data to apply the data to one of a first bit line and a first bit line bar, and a first precharge MOS transistor having a second-type channel for equalizing voltage levels of the first bit line and the first bit line bar; a first second-type well including a first sense amplifying MOS transistor having a first-type channel for sensing and amplifying the signal difference between the first bit line and the first bit line bar, and a first connection MOS transistor; and a second first-type well including a second sense amplifying MOS transistor having a second-type channel for sensing and amplifying the signal difference between the first bit line and the first bit line bar.

FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device; and,more particularly, to a semiconductor memory device for efficientlyoperating under a low power supply voltage condition.

DESCRIPTION OF RELATED ARTS

FIG. 1 is a block diagram showing a core area of a conventionalsemiconductor memory device.

As shown, the conventional semiconductor memory device includes a rowaddress input unit 20, a column address input unit 30, a cell area 100and a data input/output unit 40.

The row address input unit 20 receives a row address and decodes the rowaddress to output the decoded row address to the cell area 100. Thecolumn address input unit 30 receives a column address and decodes thecolumn address to output the decoded column address to the cell area100. The data input/output unit 40 outputs data stored in the cell area100 and delivers data inputted through a data pad/pin into the cell area100.

The cell area 100 includes a plurality of cell arrays, e.g., 110, 120,130 and 140 and a plurality of sense amplifying blocks, e.g., 150 and160. Each of the plurality of cell arrays 110 to 140 includes aplurality of unit cells, each for storing data. Each of the bit linesense amplifying blocks 150 and 160 amplifies the data outputted fromthe plurality of cell arrays 110 to 140 to output the amplified data tothe data input/output unit 40.

As described above, during a read operation, each of the bit line senseamplifying blocks 150 and 160 amplifies the data outputted from theplurality of cell arrays 110 to 140 to output the amplified data to thedata input/output unit 40. Otherwise, during a write operation, each ofthe bit line sense amplifying blocks 150 and 160 latches the dataoutputted from the data input/output unit 40 to output the latched datato the plurality of cell arrays 110 to 140.

FIG. 2 is a block diagram depicting a detailed structure of the cellarea 100 shown in FIG. 1.

As shown, in a first cell array 110, a plurality of unit cells, e.g.,CELL1, CELL2 and CELL3, are provided with every intersection between aplurality of bit line pairs, e.g., BL and /BL, and a plurality of wordlines, e.g., WL0 to WL5. Herein, each unit cell is constituted with acapacitor and a transistor.

For instance, a first cell CELL1 includes a first capacitor C0 and afirst MOS transistor M0. The first capacitor C0 is coupled between thefirst MOS transistor M0 and a plate line PL. The first MOS transistor M0is coupled between the first capacitor C0 and a bit line BL and has agate coupled to a first word line WL0.

The first cell CELL1 and a second cell CELL2 respectively coupled to thefirst word line WL0 and a second word line WL1 and neighbored with eachother are commonly connected to the bit line BL; and the bit line BL iscoupled to a sense amplifier 152a included in the bit line senseamplifying block 150.

In case of reading data stored in the first cell CELL1, the first wordline WL0 is selected and activated; then, as a result, the first MOStransistor M0 is turned on. The data stored in the first capacitor C0 isdelivered into the bit line BL.

The sense amplifier 152a senses and amplifies the data by using apotential difference between the bit line BL receiving the datadelivered through the first MOS transistor M0 and a bit line bar /BLreceiving no data outputted from any cell included in the first cellarray 110.

After sensing and amplifying operations by the sense amplifier 152a, theamplified data is outputted through a local data bus line pair LDB andLDBB to the external circuit.

At this time, the sense amplifier 152a senses and amplifies the data onthe bit line bar /BL as well as the data on the bit line BL to therebytransfer the data pair to the external circuit through the local databus line pair LDB and LDBB.

That is, if the first cell CELL1 stores data being a logic high level“1”, i.e., the first capacitor C0 is charged, the bit line BL has avoltage level of a source voltage VDD and the bit line bar /BL has avoltage level of a ground voltage GND after the sensing and amplifyingoperations. Otherwise, if the first cell CELL1 stores data being a logiclow level “0”, i.e., the first capacitor C0 is discharged, the bit lineBL has a voltage level of the ground voltage GND and the bit line bar/BL has a voltage level of the source voltage VDD after the sensing andamplifying operations.

Since an amount of charge stored in each capacitor of unit cells is alittle, the charge should be restored in the capacitor of each originalunit cell after the charge is delivered into the bit line BL. Aftercompleting the restoration by using the sensed data of the senseamplifier, a word line corresponding to the original unit cell isinactivated.

In case of reading data stored in a third cell CELL3, the third wordline WL2 is selected and activated; then, as a result, the third MOStransistor M2 is turned on. The data stored in the third capacitor C2 isdelivered into the bit line bar /BL. The sense amplifier 152a senses andamplifies the data by using the potential difference between the bitline bar /BL receiving the data delivered through the third MOStransistor M2 and the bit line BL receiving no data outputted from anycell included in the first cell array 110.

Further, in the write operation, i.e., when an inputted data is storedin the cell array, a word line corresponding to inputted row and columnaddresses is activated and, then, data stored in a cell coupled to theword line is sensed and amplified by the sense amplifier 152a. Afterthen, the amplified data is substituted with the inputted data. That is,the inputted data is latched in the sense amplifier 152a. Next, theinputted data is stored in the unit cell corresponding to the activatedword line. If it is completed to store the inputted data in the unitcell, the word line corresponding to the inputted row and columnaddresses is inactivated.

FIG. 3 is a block diagram describing a connection between each cellarray and each sense amplifying block included in the cell area 100shown in FIG. 1. Particularly, the conventional semiconductor memorydevice has a shared bit line sense amplifier structure. Herein, theshared bit line sense amplifier structure means that two neighbor cellarrays are coupled to one sense amplifying block.

As shown, there are a plurality of cell arrays 110, 130 and 180 and aplurality of sense amplifying blocks 150 and 170. The first senseamplifying block 150 is coupled to the first cell array 110 and thesecond cell array 130; and the second sense amplifying block 170 iscoupled to the second cell array 130 and the fifth cell array 180.

Herein, each of the plurality of sense amplifying blocks 150 and 170 hasa plurality of sense amplifiers. The number of plural sense amplifierscorresponds to the number of the bit line pair coupled to one cellarray.

On the other hand, in case of the shared bit line sense amplifierstructure, the number of plural sense amplifiers corresponds to thenumber of two bit line pairs because two cell arrays hold one senseamplifying block in common for implementing a higher integrated circuit.

In detail, referring to FIG. 3, under the shared bit line senseamplifier structure, the first sense amplifier 150 is provided with thefirst and the second cell arrays 110 and 130 in common.

Under the shared bit line sense amplifier structure, the first senseamplifying block 150 further includes first and second connection blocks151 and 153. Since the bit line sense amplifying block is commonlycoupled to two neighbor cell arrays 110 and 130, there should be controlfor connecting or disconnecting the first sense amplifying block 150 toone of the two neighbor cell arrays 110 and 130. Each of the first andthe second connection blocks 151 and 153 has a plurality of switchingunits, e.g., transistors. The plurality of transistors, e.g., MN1 toMN4, in the first connection block 151 is turned on or off based on afirst connection control signal BISH1; and the plurality of transistors,e.g., MN5 to MN8, in the second connection block 153 is turned on or offbased on a second connection control signal BISL1.

For instance, if the first connection control signal BISH1 is activated,all transistors included in the first connection block 151 is turned on,that is, the first cell array 110 is coupled to the sense amplifierblock 152 of the first sense amplifying block 150. Otherwise, if thesecond connection control signal BISL1 is activated, all transistorsincluded in the second connection block 153 is turned on, that is, thesecond cell array 130 is coupled to the sense amplifier block 152 of thefirst sense amplifying block 150.

Likewise, another sense amplifying block 170 includes a plurality ofsense amplifiers and two connection blocks controlled in response toother connection control signals BISH2 and BISL2 for connecting ordisconnecting a sense amplifier block of the bit line sense amplifyingblock 170 to one of the two neighbor cell arrays 130 and 180.

Moreover, each sense amplifying block, e.g., 150 and 170, furtherincludes a precharge block and a data output block besides the first andthe second connection blocks 151 and 153 and sense amplifiers.

FIG. 4 is a block diagram depicting the first sense amplifying block 150shown in FIG. 2.

As shown, the bit line sense amplifying block 150 includes first andsecond connection blocks 151a and 153a, a sense amplifier 152a, aprecharge block 155a, first and second equalization blocks 154a and 157aand a data output block 156a.

The sense amplifier 152a amplifies the potential difference between thebit line BL and the bit line bar /BL based on first and second senseamplifier power supply signals SAP and SAN. The precharge block 155aprecharges the bit line pair BL and /BL as a bit line precharge voltageVBLP, enabled by a precharge signal BLEQ activated when the senseamplifier 152a is inactivated. The first equalization block 154a makes avoltage level of the bit line BL be same to a voltage level of the bitline bar /BL in response to the precharge signal BLEQ, wherein the bitline pair BL and /BL is coupled to the first cell array 110 (not shown).Similar to the first equalization block 154a, the second equalizationblock 157a is also used for making a voltage level of the bit line BL besame to a voltage level of the bit line bar /BL in response to theprecharge signal BLEQ, wherein the bit line pair BL and /BL is coupledto the second cell array 130 (not shown). Lastly, the data output block156a outputs data amplified by the sense amplifier 152a to the localdata bus line pair LDB and LDBB based on a column control signal YIgenerated from the column address.

Herein, the bit line sense amplifying block 150 further includes firstand second connection blocks 151a and 153a, each for connecting ordisconnecting the sense amplifier 152a to one of neighbor cell arraysrespectively based on first and second connection control signals BISHand BISL.

FIG. 5 is a waveform showing an operation of the conventionalsemiconductor memory device. Hereinafter, referring to FIGS. 1 to 5, theoperation of the conventional semiconductor memory device is describedin detail.

As shown, the read operation can be split into four steps: a prechargestep, a read step, a sense step and a restore step. Likewise, the writeoperation is very similar to the read operation except that the writeoperation includes a write step instead of the read step in the readoperation and, more minutely, a sensed and amplified data is notoutputted but an inputted data from an external circuit is latched inthe sense amplifier during the sense step.

Hereinafter, it is assumed that a capacitor of a unit cell is charged,i.e., stores a logic high level “1”. Also, it is assumed that during theread operation, the first connection block 151a is enabled and thesecond connection block 153a is disabled so that the sense amplifier152a is coupled to the first cell array 110.

In the precharge step, the bit line BL and the bit line bar /BL areprecharged by the bit line precharge voltage VBLP. At this time, allword lines are inactivated. Generally, the bit line precharge voltageVBLP is a half of a core voltage VCORE, i.e., VCORE/2=VBLP.

In the precharge step, the precharge signal BLEQ is activated as a logichigh level so that the first and the second equalization blocks 154a and157a are also enabled. Thus, the bit line BL and the bit line bar /BLare percharged as the half of the core voltage VCORE. Herein, the firstand the second connection block 151a and 153a are also activated, i.e.,all transistors included in the first and the second connection block151a and 153a are turned on.

As shown in FIG. 5, a symbol ‘SN’ means a potential level charged in thecapacitor of the unit cell. During the precharge step, ‘SN’ has a levelof the core voltage VCORE as a logic high level “1”.

In the read step, a read command is inputted and carried out. Herein,the first connection block 151a is coupled to the first cell array 110and the second connection block 153a is coupled to the second cell array130. As a result, the sense amplifier 152a is coupled to the first cellarray 110 and isolated from the second cell array 130 because the firstconnection block 151a is activated and the second connection block 153ais inactivated.

In addition, the word line corresponding to the inputted row and columnaddresses is activated as a high voltage VPP until the restore step.Herein, the reason why the word line is activated as the high voltageVPP higher than the source voltage VDD that data stored in a capacitorwith the logic high level “1” is reduced by the threshold voltages of aplurality of NMOS transistors constituting the unit cell duringtransferring to the bit line BL.

As the source voltage VDD of the semiconductor memory device becomeslower, an operating speed becomes faster. Accordingly, the high voltageVPP, which is higher than the core voltage VCORE supplied with the cellarea of the semiconductor memory device, is generated for activating theword lines. As a result, it is possible to activate the word lines at ahigh speed.

If the word line is activated, a plurality of MOS transistors within theunit cell corresponding to the word line is turned on; and the datastored in the capacitor of the unit cell is delivered into the bit lineBL.

Thus, the bit line BL precharged as the half of the core voltage isboosted up by a predetermined voltage level ΔV. Herein, though thecapacitor is charged as the core voltage VCORE, a voltage level of thebit line BL is increased not to the core voltage VCORE but to thepredetermined voltage level ΔV because a capacitance Cc of the capacitoris smaller than a parasitic capacitance Cb of the bit line BL.

Referring to FIG. 5, in the read step, it is understood that the voltagelevel of the bit line BL is increased by the predetermined voltage levelΔV from the core voltage VCORE. At the same time, a voltage level of thesymbol ‘SN’ is also increased to the predetermined voltage level ΔV fromthe core voltage VCORE.

At this time, i.e., when the data is delivered into the bit line BL, nodata is delivered into the bit line bar /BL and, then, the bit line pairBL and /BL maintains a level of the half of the core voltage VCORE.

Next, in the sense step, the first sense amplifier power supply signalSAP is supplied with the core voltage VCORE and the second senseamplifier power supply signal SAN is supplied with the ground voltageGND. Then, the sense amplifier can amplify a voltage difference, i.e.,the potential difference, between the bit line BL and the bit line bar/BL by using the first and the second sense amplifier power supplysignals SAP and SAN. At this time, a relatively high side between thebit line BL and the bit line bar /BL is amplified to the core voltageVCORE; and the other side, i.e., a relatively low side between the bitline BL and the bit line bar /BL, is amplified to the ground voltageGND.

Herein, the voltage level of the bit line BL is higher than that of thebit line bar /BL. That is, after amplifying the bit line BL and the bitline bar /BL, the bit line BL is supplied with the core voltage VCOREand the bit line bar /BL is supplied with the ground voltage GND.

Lastly, in the restore step, the data outputted from the capacitorduring the read step for boosting up the bit line BL by thepredetermined voltage level ΔV is restored in the original capacitor.That is, the capacitor is re-charged. After the restore step, the wordline corresponding to the capacitor is inactivated.

Then, the conventional semiconductor memory device carries out theprecharge step again. Namely, the first and the second sense amplifierpower supply signals SAP and SAN are respectively supplied with the halfof the core voltage VCORE. Also, the precharge signal BLEQ is activatedand inputted to the first and the second equalization blocks 154a and157a and the precharge block 155a. At this time, the sense amplifier152a is coupled to the two neighbor cell arrays, e.g., 110 and 130, bythe first and the second connection blocks 151a and 153a.

As a design technology for a semiconductor memory device is rapidlydeveloped, a voltage level of a source voltage for operating thesemiconductor memory device becomes lower. However, though the voltagelevel of the source voltage becomes lower, it is requested that anoperation speed of the semiconductor memory device becomes faster.

For achieving the request about the operation speed of the semiconductormemory device, the semiconductor memory device includes an internalvoltage generator for generating a core voltage VCORE having a lowervoltage level than the source voltage VDD and a high voltage VPP havinga higher voltage level than the core voltage VCORE.

Until now, a requested operation speed can be achieved by implementing anano-scale technology for manufacturing the semiconductor memory devicethrough using above described manner for overcoming a decrease of thevoltage level of the source voltage VDD without any other particularmethod.

For example, through a voltage level of the source voltage is decreasedfrom about 3.3 V to about 2.5 V or under 2.5 V, the requested operationspeed can be achieved if the nano-scale technology is implemented basedon from about 500 nm to about 100 nm. That is, as the nano-scaletechnology is upgraded, i.e., developed, a power consumption of afabricated transistor included in the semiconductor memory device isreduced and, if the voltage level of the source voltage is notdecreased, an operation speed of the fabricated transistor becomesfaster.

However, on the nano-technology based on under 100 nm, it is verydifficult to develop the nano-technology. That is, there is a limitationfor integrating the semiconductor memory device more and more.

Also, a requested voltage level of the source voltage becomes lower,e.g., from about 2.0 V to about 1.5 V or so far as about 1.0 V. Thus,the request about the source voltage cannot be achieved by onlydeveloping the nano-technology.

If a voltage level of the supply voltage inputted to the semiconductormemory device is lower than a predetermined voltage level, an operatingmargin of each transistor included in the semiconductor memory device isnot sufficient; and, as a result, a requested operation speed is notsatisfied and an operation reliability of the semiconductor memorydevice is not guaranteed.

Also, the sense amplifier needs more time for stably amplifying avoltage difference between the bit line BL and the bit line bar /BLbecause a predetermined turned-on voltage, i.e., a threshold voltage, ofthe transistor is remained under a low supply voltage.

Moreover, if a noise is generated at the bit line pair BL and /BL, eachvoltage level of the bit line BL and the bit line bar /BL is fluctuated,i.e., increased or decreased by a predetermined level on the half of thecore voltage VCORE. That is, as the voltage level of the source voltagebecomes lower, a little noise can seriously affect the operationreliability of the semiconductor memory device.

Therefore, there is a limitation for decreasing a voltage level of thesource voltage under a predetermined level.

In addition, as the semiconductor memory device is more integrated, asize of the transistor becomes smaller and a distance between a gate ofthe transistor and the bit line gets near more and more. As a result, ableed current is generated. Herein, the bleed current means a kind ofleakage current between the gate of the transistor and the bit linebecause of a physical distance between the gate of the transistor andthe bit line under a predetermined value.

FIG. 6 is a cross-sectional view describing a unit cell of thesemiconductor memory device in order to show a cause of the bleedcurrent.

As shown, the unit cell includes a substrate 10, an device isolationlayer 11, source and drain regions 12a and 12b, a gate electrode 13, acapacitor 14 to 16, a bit line 17 and insulation layers 18 and 19.Herein, the symbol ‘A’ means a distance between the gate electrode 13 ofthe transistor and the bit line 17.

As it is rapidly developed the nano-technology for manufacturing thesemiconductor memory device, the distance between the gate electrode 13of the transistor and the bit line 17, i.e., ‘A’, becomes shorter.

In the precharge step, the bit line BL is supplied with the half of thecore voltage and the gate electrode 13, i.e., a word line, is suppliedwith the ground voltage.

If the bit line 17 and the gate electrode 13 in the unit cell areelectronically short since an error is occurred under a manufacturingprocess, a current is flown continuously during the precharge step and apower consumption is increased. In this case, the semiconductor memorydevice includes a plurality of additional unit cells for substitutingthe unit cell where the bit line and the gate electrode areshort-circuited. At this time, unit cells having a defect aresubstituted with preliminary unit cells in word line basis.

Otherwise, if there is no error under the manufacturing process, i.e.,the bit line 17 and the gate electrode 13 in a unit cell are notelectronically short-circuited in any unit cell of the semiconductormemory device, there is no bleed current. However, if the distancebetween the gate electrode 13 of the transistor and the bit line 17,i.e., ‘A’, is too short without any error under the manufacturingprocess, the bleed current is generated and flown.

Recently, how to operate a semiconductor memory device under a low powercondition is very important. If above described bleed current isgenerated, it is not appreciate that the semiconductor memory devicehaving the bleed current is applied to a system though the semiconductormemory device can be normally operated.

For reducing an amount of the bleed current, it is suggested that aresistor is added between the gate electrode of the transistor and thebit line. However, although the resistor can reduce little amount of thebleed current, this is not effective and essential for reducing andprotecting a flow of the bleed current.

Further, the conventional semiconductor memory device has anotherproblem. That is, there exists a bleed current between a sense amplifierand a disconnected cell array. As above-mentioned, when one cell arrayis connected to the sense amplifier, the other cell array isdisconnected from the cell array by turning off a MOS transistorincluded in the corresponding connection block. Herein, a bit line pairof the disconnected cell array has a voltage level of about the half ofthe source voltage VDD; and one bit line and the other bit line of thesense amplifier have a voltage level of the source voltage VDD and avoltage level of the ground voltage GND respectively.

Accordingly, even though the connection block is turned off, the bleedcurrent is flown from the disconnected cell array to the sense amplifiersuch as “Sub_Vt Leak Current” shown in FIG. 4. This bleed current causesa current increase during a data access operation.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide asemiconductor memory device for operating in a fast speed under a lowpower condition and protecting a bleed current from generating tothereby reduce a power consumption. In particular, there is provided alayout of a sense amplifying block of the semiconductor memory device.

In accordance with an aspect of the present invention, there is provideda semiconductor memory device having a folded bit line structure andoperating with a source voltage and a ground voltage, including: a firstfirst-type well including a first cell array for providing data to afirst bit line or a first bit line bar selected among a plurality of bitlines, and a first precharge MOS transistor having a second-type channelfor equalizing voltage levels of the first bit line and the first bitline bar during a precharge period; a first second-type well including afirst sense amplifying MOS transistor having a first-type channel amonga plurality of sense amplifying MOS transistors for sensing andamplifying a signal difference between the first bit line and the firstbit line bar, and a first connection MOS transistor having a first-typechannel for connecting or disconnecting the first bit line and the firstbit line bar to or from the first sense amplifying MOS transistor; and asecond first-type well including a second sense amplifying MOStransistor having a second-type channel among the plurality of senseamplifying MOS transistors for sensing and amplifying the signaldifference between the first bit line and the first bit line bar.

In accordance with another aspect of the present invention, there isprovided a semiconductor memory device device having a folded bit linestructure and operating with a source voltage and a ground voltage,including: a first well including a first cell array for providing datato a first bit line or a first bit line bar selected among a pluralityof bit lines; a second well including a second cell array for providingdata to a second bit line or a second bit line bar selected among theplurality of bit lines; a third well including a first sense amplifyingMOS transistor having a first-type channel among a plurality of senseamplifying MOS transistors provided in a bit line sense amplifier, afirst connection unit for connecting or disconnecting the first bit lineand the first bit line bar to or from the bit line sense amplifier, anda second connection unit for connecting or disconnecting the second bitline and the second bit line bar to or from the bit line senseamplifier; and a fourth well including a second sense amplifying MOStransistor having a second-type channel among the plurality of senseamplifying MOS transistors provided in the bit line sense amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention willbecome apparent from the following description of preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing a core area of a conventionalsemiconductor memory device;

FIG. 2 is a block diagram depicting a detailed structure of the cellarea shown in FIG. 1;

FIG. 3 is a block diagram describing a connection between each cellarray and each sense amplifying block included in the cell area shown inFIG. 1;

FIG. 4 is a block diagram depicting the bit line sense amplifying blockshown in FIG. 2;

FIG. 5 is a waveform showing an operation of the conventionalsemiconductor memory device;

FIG. 6 is a cross-sectional view describing a unit cell of thesemiconductor memory device in order to show a cause of a bleed current;

FIG. 7 is a block diagram showing a semiconductor memory device inaccordance with an embodiment of the present invention;

FIG. 8 is a schematic circuit diagram depicting a sense amplifying blockof the semiconductor memory device shown in FIG. 7;

FIG. 9 is a timing diagram showing an operation of the semiconductormemory device shown in FIGS. 7 and 8;

FIG. 10 is a layout showing the bit line sense amplifying block of thesemiconductor memory device shown in FIG. 8; and

FIG. 11 is cross-sectional view describing the layout of the bit linesense amplifying block shown in FIG. 10.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a semiconductor memory device in accordance with thepresent invention will be described in detail referring to theaccompanying drawings.

FIG. 7 is a block diagram showing a semiconductor memory device inaccordance with an embodiment of the present invention. FIG. 8 is aschematic circuit diagram depicting a sense amplifying block of thesemiconductor memory device shown in FIG. 7.

As shown, the semiconductor memory device according to the presentinvention has a folded bit line structure and operates by receiving asource voltage VDD and a ground voltage GND and includes a plurality ofunit cells, each of which has an NMOS transistor and a capacitor.

In detail, the semiconductor memory device includes a first cell array300a, a bit line sense amplifying block 200 and a first reference cellblock 400a. The first cell array 300a stores data and outputs the datato a first bit line BL or a first bit line bar /BL selected among aplurality of bit lines provided in the plurality of unit cells. The bitline sense amplifying block 200 has a bit line sense amplifier 210 forsensing and amplifying a potential difference between data signalsloaded on the first bit line BL and the first bit line bar /BL. Thefirst reference cell block 400a transfers a reference signal to thefirst bit line bar /BL when the data is outputted to the first bit lineBL or to the first bit line BL when the data signal is outputted to thefirst bit line bar /BL.

The bit line sense amplifying block 200 further includes a firstprecharge unit 220a for equalizing the potential difference between thedata signals of the first bit line BL and the first bit line bar /BLcoupled to the first cell array 300a at a precharge operation. That is,during the precharge operation, the first precharge unit 220a floats thefirst bit line BL and the first bit line bar /BL by not proving aprecharge voltage to the first bit line BL and the first bit line bar/BL.

The first reference cell block 400a includes a reference capacitorTOP_RC, a first reference switching NMOS transistor TOP_NM1 and a secondreference switching NMOS transistor TOP_NM2.

The reference capacitor TOP_RC has one terminal coupled to a referencepower supply terminal TOP_RPL. The first reference switching NMOStransistor TOP_NM1 is located between the other terminal of thereference capacitor TOP_RC and the first bit line BL so as to connectthe other terminal of the reference capacitor TOP_RC to the first bitline BL when the data signal is delivered to the first bit line bar /BLwhen the data signal is delivered to the first bit line BL. The secondreference switching NMOS transistor TOP_NM2 is located between the otherterminal of the reference capacitor TOP_RC and the first bit line bar/BL so as to connect the other terminal of the reference capacitorTOP_RC to the first bit line bar /BL when the data signal is deliveredto the first bit line BL.

Herein, a capacitance of the reference capacitor TOP_RC is substantiallysame to that of a cell capacitor of the unit cell, e.g., CAP1 and CAP2,included in the first cell array 300a. A voltage level at the referencepower supply terminal TOP_RPL can be one of the ground voltages, a halfof the source voltage VDD and the source voltage VDD.

The number of reference capacitors included in the first reference cellblock 400a corresponds to the number of bit line pairs included in acorresponding cell array, i.e., the first cell array 300a. For instance,if the first cell array 300a includes 256 bit line pairs, the firstreference cell block 400a includes 256 reference capacitors. Eachreference capacitor is coupled to one of a corresponding bit line pairwhich carries no data signal to thereby deliver the reference signalstored in the reference capacitor to the coupled bit line.

Meanwhile, the bit line sense amplifying block 200 further includes afirst connection unit 250a connected between the bit line senseamplifier 210 and the first precharge unit 220a for connecting ordisconnecting the first bit line BL and the first bit line bar /BLincluded in the first cell array 300a to/from the bit line senseamplifier 210.

The first connection unit 250a includes a first connection PMOStransistor TBH1 and a second connection PMOS transistor TBH2. The firstconnection PMOS transistor TBH1 connects the first bit line BL to thebit line sense amplifier 210 in response to a first connection controlsignal BISH. The second connection PMOS transistor TBH2 connects thefirst bit line bar /BL to the bit line sense amplifier 210 in responseto the first connection control signal BISH.

Also, the bit line sense amplifying block 200 further includes a firstauxiliary bit line sense amplifier 230a for amplifying and maintaining avoltage level of a lower one of the first bit line BL and the first bitline bar /BL included between the first cell array 300a and the firstconnection unit 250a as a voltage level of the ground voltage GND. Afirst bit line control signal BLPD_H inputted to the first auxiliary bitline sense amplifier 230a has a voltage level of the ground voltage GNDwhile the bit line sense amplifier 210 is operated.

In detail, the first auxiliary bit line sense amplifier 230a includes afirst auxiliary NMOS transistor TSB1 and a second auxiliary NMOStransistor TSB2. The first auxiliary NMOS transistor TSB1 has oneterminal for receiving the first bit line control signal BLPD_H which isactivated when the bit line sense amplifier 210 is enabled, and theother terminal coupled to the first bit line BL which is connectedbetween the first cell array 300a and the first connection unit 250a. Agate of the first auxiliary NMOS transistor TSB1 is coupled to the firstbit line bar /BL connected between the first cell array 300a and thefirst connection unit 250a. Similarly, the second auxiliary NMOStransistor TSB2 has one terminal for receiving the first bit linecontrol signal BLPD_H which is activated when the bit line senseamplifier 210 is enabled, and the other terminal coupled to the firstbit line bar /BL connected between the first cell array 300a and thefirst connection unit 250a. A gate of the second auxiliary NMOStransistor TSB2 is coupled to the first bit line BL connected betweenthe first cell array 300a and the first connection unit 250a.

The first precharge unit 220a includes a first precharge NMOS transistorTP1 for equalizing voltage levels of the first bit line BL and first bitline bar /BL in the first cell array 300a based on a first prechargesignal BLEQ_H.

Meanwhile, in accordance with the preferred embodiment, a cell array hasa folded bit line structure and also has a shared bit line structure,i.e., a bit line sense amplifier is commonly coupled two neighboringcell arrays. Therefore, the semiconductor memory device further includesa second cell array 300b coupled to the other side of the bit line senseamplifier 210; and a second connection unit 250b for connecting ordisconnecting the second cell array 300b to/from bit line senseamplifier 210.

Similar to the first cell array 300a, the second cell array 300b storesdata and outputs the data to a selected second bit line BOT_BL or asecond bit line bar /BOT_BL. The second connection unit 250b connects ordisconnects the second bit line BOT_BL and the second bit line bar/BOT_BL to/from the bit line sense amplifier 210.

Herein, the semiconductor memory device further includes a secondreference cell block 400b and a second precharge unit 220b. The secondreference cell block 400b transfers a reference signal to the second bitline bar /BOT_BL when the data signal is outputted to the second bitline BOT_BL or to the second bit line BOT_BL when the data signal isoutputted to the second bit line bar /BOT_BL; and the second prechargeunit 220b equalizes a potential difference between the second bit lineBOT_BL and the second bit line bar /BOT_BL included in the second cellarray 300b during the precharge operation. That is, the second prechargeunit 220b floats the second bit line BOT_BL and the second bit line bar/BOT_BL by not proving the precharge voltage to the second bit lineBOT_BL and the second bit line bar /BOT_BL during the prechargeoperation.

Meanwhile, the bit line sense amplifying block 200 further includes asecond auxiliary bit line sense amplifier 230b connected between thesecond cell array 300b and the bit line sense amplifier 210 foramplifying and maintaining a voltage level of a lower one of the secondbit line BOT_BL and the second bit line bar /BOT_BL included between thesecond cell array 300b and the second connection unit 250b as a voltagelevel of the ground voltage GND.

In detail, the second auxiliary bit line sense amplifier 230b includes athird auxiliary NMOS transistor TSB3 and a fourth auxiliary NMOStransistor TSB4. The third auxiliary NMOS transistor TSB3 has oneterminal for receiving a second bit line control signal BLPD_L which isactivated when the bit line sense amplifier 210 is enabled, and theother terminal coupled to the second bit line BOT_BL connected betweenthe second cell array 300b and the second connection unit 250b. A gateof the third auxiliary NMOS transistor TSB3 is coupled to the second bitline bar /BOT_BL connected between the second cell array 300b and thesecond connection unit 250b. Similarly, the fourth auxiliary NMOStransistor TSB4 has one terminal for receiving the second bit linecontrol signal BLPD_L which is activated when the bit line senseamplifier 210 is enabled, and the other terminal coupled to the secondbit line bar /BOT_BL connected between the second cell array 300b andthe second connection unit 250b. A gate of the fourth auxiliary NMOStransistor TSB4 is coupled to the second bit line BOT_BL connectedbetween the second cell array 300b and the second connection unit 250b.

The second precharge blocks 220b includes a second precharge NMOStransistor TP2 for equalizing voltage levels of the second bit lineBOT_BL and the second bit line bar /BOT_BL in the second cell array 300bbased on a second precharge signal BLEQ_L.

Meanwhile, the bit line sense amplifier 210 includes first and secondsense amplifying PMOS transistors TS1 and TS2, and first and secondsense amplifying NMOS transistors TS3 and TS4.

A gate of the first sense amplifying PMOS transistor TS1 is connected tothe first bit line bar /BL by the first connection unit 250a or to thesecond bit line bar /BOT_BL by the second connection unit 250b. Oneterminal of the first sense amplifying PMOS transistor TS1 receives afirst sense amplifier power supply signal SAP and the other terminal isconnected to the first bit line BL by the first connection unit 250a orto the second bit line BOT_BL by the second connection unit 250b.

Similarly, a gate of the second sense amplifying PMOS transistor TS2 isconnected to the first bit line BL by the first connection unit 250a orto the second bit line BOT_BL by the second connection unit 250b. Oneterminal of the second sense amplifying PMOS transistor TS2 receives thefirst sense amplifier power supply signal SAP and the other terminal isconnected to the first bit line bar /BL by the first connection unit250a or to the second bit line bar /BOT_BL by the second connection unit250b.

A gate of the first sense amplifying NMOS transistor TS3 is connected tothe first bit line bar /BL by the first connection unit 250a or to thesecond bit line bar /BOT_BL by the second connection unit 250b. Oneterminal of the first sense amplifying NMOS transistor TS3 receives asecond sense amplifier power supply signal SAN and the other terminal isconnected to the first bit line BL by the first connection unit 250a orto the second bit line BOT_BL by the second connection unit 250b.

Similarly, a gate of the second sense amplifying NMOS transistor TS4 isconnected to the first bit line BL by the first connection unit 250a orto the second bit line BOT_BL by the second connection unit 250b. Oneterminal of the second sense amplifying NMOS transistor TS4 receives thesecond sense amplifier power supply signal SAN and the other terminal isconnected to the first bit line bar /BL by the first connection unit250a or to the second bit line bar /BOT_BL by the second connection unit250b.

In accordance with the embodiment of the present invention, the firstsense amplifier power supply signal SAP is supplied with the sourcevoltage VDD and the second sense amplifier power supply signal SAN issupplied with a low voltage VBB. Herein, the low voltage VBB has a lowervoltage level than the ground voltage GND having a voltage level ofabout −0.5 V. As described above, the bit line sense amplifier 210performs a sensing and amplifying operation by using the low voltage VBBand the source voltage VDD.

Meanwhile, the semiconductor memory device further includes a datainput/output unit 240 for outputting data sensed and amplified by thebit line sense amplifier 210 through a local data bus line pair LDB andLDBB to an external circuit, and for delivering data inputted from theexternal circuit via the local data bus line pair LDB and LDBB to thebit line sense amplifier 210.

In detail, the data input/output unit 240 includes first and secondinput/output MOS transistors T01 and T02. A gate of the firstinput/output MOS transistor T01 receives a column control signal YI. Oneterminal of the first input/output MOS transistor T01 is connected tothe first and the second bit lines BL and BOT_BL and the other terminalof the first input/output MOS transistor T01 is coupled to a first localdata bus line LDB. Similarly, a gate of the second input/output MOStransistor T02 receives the column control signal YI; and one terminalof the second input/output MOS transistor T02 is connected to the firstand the second bit line bars /BL and /BOT_BL and the other terminal ofthe second input/output MOS transistor T02 is coupled to a second localdata bus line LDBB.

FIG. 9 is a timing diagram showing an operation of the semiconductormemory device shown in FIGS. 7 and 8.

Referring to FIGS. 7 to 9, the operations of the semiconductor memorydevice according to the embodiment of the present invention aredescribed below.

In accordance with the preferred embodiment of the present invention,the semiconductor memory device includes a reference cell block to floata bit line and a bit line bar by not proving the precharge voltage tothe bit line and the bit line bar during a precharge step.

In addition, in the preferred embodiment of the present invention, thebit line sense amplifier performs a sensing and amplifying operation bynot using the source voltage VDD and the ground voltage GND, but usingthe source voltage VDD and the low voltage VBB having the lower voltagelevel than the ground voltage GND, i.e., the voltage level of about −0.5V, and the source voltage VDD.

Meanwhile, if the voltage level of the source voltage VDD is moredecreased, it is possible that an absolute quantity of the sourcevoltage VDD is equal to that of the low voltage VBB. In this case, avoltage level of the precharge voltage of the bit line can be maintainedas the ground voltage GND by making voltage levels of two bit lines besame after a sensing operation of the bit line sense amplifier.

Meanwhile, as above-mentioned, the semiconductor memory device furtherincludes an auxiliary bit line sense amplifier for maintaining a voltagelevel of a neighboring bit line pair as a half of the source voltage VDDby using the reference cell block and a precharge unit when the bit linesense amplifier is operated for a data access.

Hereinafter, the above-mentioned operations of the semiconductor memorydevice are described in detail. Herein, it is assumed that a readoperation is performed for reading a high-level data ‘1’, and the datais transferred to the first bit line BL.

A data access operation of the semiconductor memory device can be splitinto four steps: a precharge step, a read/write step, a sense step and arestore step.

At the precharge step, the first and the second precharge signals BLEQ_Hand BLEQ_L are activated and maintain an enable state as a voltage levelof a high voltage VPP so that voltage levels of a first bit line pair BLand /BL is equalized and voltage levels of a second bit line pair BOT_BLand /BOT_BL is also equalized.

As above-mentioned, in the present invention, since the prechargevoltage is not supplied with the first bit line pair BL and /BL duringthe precharge step, the first bit line pair BL and /BL, a senseamplifier bit line pair SA_BL and SA_/BL and the second bit line pairBOT_BL and /BOT_BL is floated (t0). At this time, the first and thesecond connection units 250a and 250b are turned on; and the groundvoltage GND is supplied with all word lines to thereby maintain aninactivated state.

Accordingly, the first bit line pair BL and /BL, the sense amplifier bitline pair SA_BL and SA_/BL and the second bit line pair BOT_BL and/BOT_BL keeps a voltage level of a half of the source voltage VDD at theprecharge step by using the first and the second precharge units 220aand 220b right after a read/write operation is performed (After asensing and amplifying operation is performed by the bit line senseamplifier 210, one of a bit line pair has a voltage level of the sourcevoltage VDD and the other has a voltage level of the ground voltageGND). Thereafter, since the precharge voltage is not provided during theprecharge step, the bit line voltage level of the half of the sourcevoltage VDD is decreased as a period of the precharge step is longer. Ifthe precharge step is more continuously performed so as not to enter theread/write step, the voltage level of the first bit line pair BL and /BLand the sense amplifier bit line pair SA_BL and SA_/BL is decreased tothe ground voltage GND.

Therefore, a precharge voltage of each floated bit line has a variablevoltage level between the half of the source voltage VDD and the groundvoltage GND. As a result, a timing of performing the read/writeoperation determines the precharge voltage of each floated bit line.

Thereafter, at the read step, a single word line is selected by decodinginputted column and row addresses. All of the NMOS transistorscorresponding to the selected word line are turned on and data stored inthe cell capacitor is transferred to the first bit line BL through theturned-on NMOS transistor.

If the high-level data ‘1’ is delivered to the first bit line BL,voltage levels of the first bit line BL and the sense amplifier bit lineSA_BL, which have a voltage level between the half of the source voltageVDD and the ground voltage GND as above-mentioned, are increased by anamount of the high-level data ‘1’.

Meanwhile, a reference signal is inputted to the first bit line bar /BLand the sense amplifier bit line bar SA_/BL which have no data signal. Afirst reference word line bar /TOP_RWL having no data signal isactivated and, thus, the second reference switching NMOS transistorTOP_NM2 is turned on. Accordingly, the reference signal stored in thereference capacitor TOP_RC is transferred to the first bit line bar /BLand the sense amplifier bit line bar SA_/BL and, thus, voltage levels ofthe first bit line bar /BL and the sense amplifier bit line bar SA_/BLare increased by an amount of a predetermined voltage level.

At this time, before the reference signal is inputted, voltage levels ofthe first bit line bar /BL and the sense amplifier bit line bar SA_/BLare gradually decreased from the half of the source voltage VDD so as tohold a predetermined voltage level, and then, the voltage levels of thefirst bit line bar /BL and the sense amplifier bit line bar SA_/BL areincreased by an amount of a signal level of the reference signal.

As above-mentioned, the capacitance of the reference capacitor TOP_RC issubstantially same to that of the cell capacitor of the unit cell, e.g.,CAP1 and CAP2. A charge amount of the reference capacitor TOP_RC whichstores the reference signal is a half of a charge amount of the cellcapacitor of the unit cell, e.g., CAP1 and CAP2, which stores thehigh-level data ‘1’.

In other words, because reference power supply terminals, i.e.,HALF_VDD, TOP_RPL and BOT_RPL, receive a voltage level of a half of thesource voltage VDD, the charge amount of the reference capacitor TOP_RCwhich stores the reference signal is the half of the charge amount ofthe cell capacitor of the unit cell which stores the high-level data‘1’. At this time, each of voltage levels supplied by the referencepower supply terminals TOP_RPL and BOT_RPL is same to a voltage level ofa plate voltage PL supplied with the cell capacitor of the unit cell,e.g., CAP1 and CAP2, included in a cell array.

At this time, the voltage level can have a voltage level of the sourcevoltage VDD, a half of the source voltage VDD or the ground voltage GND.A voltage level which is same to the plate voltage PL is supplied to thereference power supply terminals TOP_RPL and BOT_RPL so that thereference signal can have a half signal level of the high-level data.

Accordingly, the signal level increase of the first bit line bar /BLwhich receives the reference signal is a half of that of the first bitline BL which receives the high-level data. For instance, when thesource voltage VDD is 1.0V and there is a voltage increase by 0.2V dueto the high-level data, the first bit line pair BL and /BL has a voltagelevel of about 0.5V at an initial state of the precharge step.Thereafter, as the precharge step is continued, it is assumed that eachof the voltage levels of the first bit line pair BL and /BL is decreasedto about 0.3V. At this time, if a read command is performed, the voltagelevel of the first bit line BL having the high-level data is increasedto about 0.5V, i.e., 0.3V+0.2V, and the voltage level of the first bitline bar /BL having the reference signal which has the half signal levelof the high-level data is increased to 0.4V, i.e., 0.3V+0.1V.

Meanwhile, the first precharge signal BLEQ_H is activated so as toenable the first precharge unit 220a during the precharge step and isinactivated so as to disable the first precharge unit 220a during theread, sense and restore steps.

Next, at the sense step, the first sense amplifier power supply signalSAP of the bit line sense amplifier 210 receives the source voltage VDDand the second sense amplifier power supply signal SAN receives a firstnegative low voltage VBB_H.

Therefore, the bit line sense amplifier 210 senses a voltage differencebetween the first bit line pair BL and /BL to thereby amplify a voltagelevel of a bit line having a higher voltage level, i.e., the first bitline BL, to a voltage level of the source voltage VDD and amplify avoltage level of a bit line having a lower voltage level, i.e., thefirst bit line bar /BL, to a voltage level of the ground voltage GND(t2).

Since the bit line sense amplifier 210 performs the amplifying operationby using the source voltage VDD and the first negative low voltageVBB_H, the amplifying operation can be performed at a high speed incomparison with using the source voltage VDD and the ground voltage GND.

Herein, a voltage level of the sense amplifier bit line bar SA_/BLincluded between the bit line sense amplifier 210 and the firstconnection unit 250a is amplified to the first negative low voltageVBB_H; however, the first bit line bar /BL included between the firstcell array 300a and the first auxiliary bit line sense amplifier 230a isamplified to the ground voltage GND. Since the first connection controlsignal BISH inputted to each gate of the first and the second connectionPMOS transistors TBH1 and TBH2 included in the first connection unit250a has a voltage level of the first negative low voltage VBB_H, eventhough the sense amplifier bit line bar SA_/BL coupled to the bit linesense amplifier 210 is amplified to the first negative low voltageVBB_H, the first bit line bar /BL coupled to the first cell array 300ais amplified to the ground voltage GND which is higher than the firstnegative low voltage VBB_H.

Similarly, the second connection unit 250b performs a clamping operationso that a voltage level of the first negative low voltage VBB_H is nottransferred to a bit line coupled to the second cell array 300b eventhough the bit line sense amplifier 210 amplifies the sense amplifierbit line bar SA_/BL to the first negative low voltage VBB_H. Also, sincea parasitic capacitance occurred in the first bit line bar /BL isrelatively larger than a sub-threshold voltage of the first and thesecond connection PMOS transistors TBH1 and TBH2 included in the firstconnection unit 250a, the first bit line bar /BL coupled to the firstcell array 300a can keep the voltage level of the ground voltage GNDduring the sense step and the restore step.

Therefore, since a bit line pair coupled to a cell array can keep thevoltage level of the ground voltage GND by preventing the first negativelow voltage VBB_H amplified by the bit line sense amplifier 210 frombeing transferred to the bit line pair, a voltage variation of each bitline is minimized. As a result, an operational speed of the bit linesense amplifier 210 can be improved and a power consumption due to thevoltage variation of each bit line coupled to each cell array can bereduced. For this, the first and the second connection units 250a and250b are provided not only for controlling the connection between thebit line sense amplifier 210 and each cell array but also for preventingthe first negative low voltage VBB_H from being transferred to the firstbit line pair BL and /BL, the second bit line pair BOT_BL and /BOT_BLincluded in each cell array.

However, the first and the second connection units 250a and 250b are notenough for stably maintaining the voltage level of the first bit linepair BL and /BL included in the cell array as the ground voltage GND.Therefore, the first and the second auxiliary bit line sense amplifiers230a and 230b are provided for maintaining the voltage level of thefirst bit line pair BL and /BL included in the first cell array 300a asthe ground voltage GND even though the sense amplifier bit line pairSA_BL and SA_/BL coupled to the bit lines sense amplifier 210 areamplified to the first negative low voltage VBB_H.

The first and the second auxiliary bit line sense amplifiers 230a and230b amplify and maintain one of the first bit line pair BL and /BLincluded in the first cell array 300a, which has a lower voltage levelthan the other, as the voltage level of the ground voltage GND while thebit line sense amplifier 210 performs the sensing and amplifyingoperation.

For example, when the bit line sense amplifier 210 amplifies a voltagelevel of the sense amplifier bit line SA_BL to the source voltage VDDand amplifies a voltage level of the sense amplifier bit line bar SA_/BLto the first negative low voltage VBB_H, the first bit line BL keeps avoltage level of the source voltage VDD and the first bit line bar /BLkeeps a voltage level of the ground voltage GND. At this time, the firstauxiliary bit line sense amplifier 230a decreases a voltage level of thefirst bit line bar /BL so as to be the ground voltage GND when a voltagelevel of the first bit line bar /BL is higher than the ground voltageGND and increases a voltage level of the first bit line bar /BL so as tobe the ground voltage GND when a voltage level of the first bit line bar/BL is lower than the ground voltage GND.

Meanwhile, the first and the second bit line control signals BLPD_H andBLPD_L respectively inputted to the first and the second auxiliary bitline sense amplifiers 230a and 230b are activated as the ground voltageGND during an activation period of the bit line sense amplifier 210,i.e., t2, t3 and t4.

As above-mentioned, gates of the first and the second auxiliary NMOStransistors TSB1 and TSB2 included in the first auxiliary bit line senseamplifier 230a are cross-coupled to the first bit line pair BL and /BL.Each one terminal of the first and the second auxiliary NMOS transistorsTSB1 and TSB2 receive the ground voltage GND as the first bit linecontrol signal BLPD_H to thereby maintain a lower voltage level of thefirst bit line pair BL and /BL as the ground voltage GND due to thecross-coupled gates of the first and the second auxiliary NMOStransistors TSB1 and TSB2.

Likewise, gates of the third and the fourth auxiliary NMOS transistorsTSB3 and TSB4 included in the second auxiliary bit line sense amplifier230b are cross-coupled to the second bit line pair BOT_BL and /BOT_BL.Each one terminal of the third and the fourth auxiliary NMOS transistorsTSB3 and TSB4 receive the ground voltage GND as the second bit linecontrol signal BLPD_L to thereby maintain a lower voltage level of thesecond bit line pair BOT_BL and /BOT_BL as the ground voltage GND due tothe cross-coupled gates of the third and the fourth auxiliary NMOStransistors TSB3 and TSB4.

Since each unit cell included in each cell array is constituted with theNMOS transistor, i.e., TC1 and TC2, and the cell capacitor, i.e., CAP1and CAP2, if the first negative low voltage VBB_H is transferred to thebit line included in the cell array when the bit line sense amplifieramplifies a bit line pair to the source voltage VDD and the firstnegative low voltage VBB_H, the NMOS transistor in the unit cell isturned on and data of an unselected unit cell may be lost. Therefore, itis required that the first negative low voltage VBB_H amplified by thebit line sense amplifier is not delivered to the bit line included inthe cell array while the bit line sense amplifier is operated.

Meanwhile, each of the first and the second connection control signalsBISH and BISL inputted to the first and the second connection unit 250aand 250b has two voltage levels: one is the first negative low voltageVBB_H having a negative voltage level whose absolute quantity is equalto each threshold voltage of a first and a fourth PMOS connectiontransistors TBH1, TBH2, TBL1 and TBL2 included in the first and thesecond connection units 250a and 250b and the other is a second negativelow voltage VBB_L having a negative voltage level whose absolutequantity is larger than that of the first to the fourth connection PMOStransistors TBH1, TBH2, TBL1 and TBL2.

The first and the second connection control signals BISH and BISL areinputted as the first negative low voltage VBB_H for equalizing voltagelevels of each bit line pair included in the first and the second cellarrays 300a and 300b, e.g., the first bit line pair BL and /BL, duringthe precharge step.

At the read step where the first cell array 300a is connected to the bitline sense amplifier 210 and the second cell array 300b is disconnectedfrom the bit line sense amplifier 210, the second connection controlsignal BISL is provided as the source voltage VDD to disable the secondconnection unit 250b and the first connection control signal BISH isactivated as a voltage level of the second negative low voltage VBB_L toenable the first connection unit 250a. Thereafter, at the sense stepwhere the bit line sense amplifier 210 senses and amplifies a voltagedifference between the sense amplifier bit line pair SA_BL and SA_/BLand the restore step, the activated first connection control signal BISHis provided as the first negative low voltage VBB_H.

As described above, during the precharge step, the relatively lower lowvoltage, i.e., the second negative low voltage VBB_L, is used for morereliable isolation between the bit line sense amplifier 210 and a bitline coupled to a cell array. Otherwise, the relatively higher lowvoltage, i.e., the first negative low voltage VBB_H, is used for theisolation between the bit line sense amplifier 210 and the bit linecoupled to the cell array. This is for the bit line sense amplifier 210,which uses the first negative low voltage VBB_H, to perform the sensingand amplifying operation more quickly when the bit line sense amplifier210 mainly performs the sensing and amplifying operation.

Thereafter, when the sensing and amplifying operation of the bit linesense amplifier 210 is completed, a column control signal YI isactivated for a predetermined time. Then, in response to the columncontrol signal YI, a data signal latched by the bit line sense amplifier210 is outputted to the local data bus line pair LDB and LDBB (t3). Atthis time, the outputted data signal is data corresponding to the readcommand.

During the restore step, the data signal is restored to an original unitcell by using the data signal latched by the bit line sense amplifier210 (t4).

When the restore step is completed, a corresponding word line, i.e., WL1and WL2, is inactivated as a voltage level of the source voltage VDD,and the first and the second sense amplifier power supply signals SAPand SAN are respectively supplied with the ground voltage GND and thehalf of the source voltage VDD so that the bit line sense amplifier 210is disabled.

In accordance with the conventional invention, since the local data busline pair LDB and LDBB is precharged to the source voltage VDD or thehalf of the source voltage VDD while data is not transferred, a voltagelevel of a bit line (the sense amplifier bit line bar SA_/BL in thiscase) amplified to the ground voltage GND by the bit line senseamplifier 210 is increased to a predetermined voltage level duringtransferring the data amplified by the bit line sense amplifier 210.Accordingly, an enough time for the restore time should be provided forthe increased voltage level of the sense amplifier bit line bar SA_/BLto be decreased to the ground voltage GND. Otherwise, a wrong data canbe restored to the original unit cell; particularly, if an original datais ‘0’, the original data is restored as ‘1’. For overcoming theabove-mentioned problem, in the conventional invention, a period of therestore step (t4) should be long.

However, in accordance with the present invention, since the senseamplifier bit line bar SA_/BL is amplified to the first negative lowvoltage VBB_H lower than the ground voltage GND by the bit line senseamplifier 210, even though a current is flown to the first bit line bar/BL coupled to the bit line sense amplifier 210 by the local data busline pair LDB and LDBB, a voltage level of the first bit line bar /BLcoupled to the bit line sense amplifier 210 is not increased or at leastnot higher than the ground voltage GND because the flown current iscompensated by the sense amplifier bit line bar SA_/BL having the firstnegative low voltage VBB_H. Accordingly, the period of the restore step(t4) can be decreased in comparison with the conventional invention.

Thereafter, when the first precharge signal BLEQ_H is activated as alogic high level, the first bit line pair BL and /BL has a same voltagelevel to be floated. Also, the first and the second connection signalsBISH and BISL are provided as the first negative low voltage VBB_H and,thus, all of the bit lines BL, SA_BL, BOT_BL, /BL, SA_/BL and /BOT_BLare connected (t5).

As above-mentioned, at the initial state of the precharge step, thefirst bit line pair BL and /BL keeps the voltage level of the half ofthe source voltage VDD; however, each voltage level of the first bitline pair BL and /BL is decreased as time passes because the first bitline pair BL and /BL is floated not receiving a particular prechargevoltage.

Meanwhile, while the first connection unit 250a is enabled, the secondreference cell block 400b and the second precharge unit 220b are enabledso that each voltage level of the second bit line pair BOT_BL and/BOT_BL is maintained as the precharge voltage. In accordance with thepresent invention, while voltage levels of a bit line pair is maintainedto have a same voltage level at the precharge step, the bit line pair isfloated not being supplied with a special precharge voltage. Therefore,there is no particular precharge voltage which all of the bit lines keepat the precharge step.

Herein, the precharge voltage means a half of the source voltage VDDwhich a bit line pair maintains when the bit line pair has a samevoltage level after one of the bit line pair has a voltage level of thesource voltage VDD and the other has a voltage level of the groundvoltage GND after performing a data read or write operation. That is,while the bit line sense amplifier 210 accesses data of a unit cell, avoltage level of the bit line pair which shares the bit line senseamplifier 210 and is not connected to the bit line sense amplifier 210is maintained as the half of the source voltage VDD by using acorresponding precharge unit and a reference cell block.

Since a voltage level of a bit line included in an inactivated cellarray is rapidly decreased due to a voltage difference between thesecond sense amplifier power supply signal SAN of the bit line senseamplifier for accessing data and a voltage level of the bit lineincluded in the inactivated cell array, the above-mentioned operation isneeded.

Although the first and the second connection unit 250a and 250b includethe first to fourth connection PMOS transistors TBH1, TBH2, TBL1 andTBL2 which receive one of the first and the second connection controlsignals BISL and BISH between the first and the second sense amplifierpower supply signals SAP and SAN and the bit line of the inactivatedcell array, and even though the PMOS transistors are turned off, asub-current still flows and the bit line included in the inactivatedcell array is rapidly decreased due to a leakage current of thesub-current. If a size of the PMOS transistor is larger, theabove-mentioned problem becomes more serious.

Generally, the semiconductor memory device keeps the precharge voltageas the half of the source voltage VDD. Herein, in the shared bit linestructure, when the bit line sense amplifier senses and amplifies avoltage difference between a bit line pair coupled to one side of thebit line sense amplifier for a data accessing, the other bit line pairwhich does not serve to access data and is coupled to the other side ofthe bit line sense amplifier keeps a precharge voltage level as the halfof the source voltage VDD. In this time, there occurs an error since theprecharge voltage level is decreased due to a voltage difference betweenthe precharge voltage and a ground voltage supply terminal of the bitline.

In accordance with the present invention, since the bit line pair whichdoes not serve to access the data is floated at the precharge step, theabove-mentioned problem does not occur. However, if the prechargevoltage is maintained as the half of the source voltage VDD, the dataaccess operation can be performed more effectively since the prechargevoltage level of the half of the source voltage VDD is the mosteffective for sensing a high-level data and a low-level data.

Since the semiconductor memory device in accordance with the presentinvention maintains a voltage level of a bit line pair which neighborswith the bit line pair served for a data access as the half of thesource voltage VDD by using the corresponding reference cell block andthe corresponding precharge unit, all of bit line pairs which neighborwith the bit line pair for data accessing can keep a voltage level ofthe half of the source voltage VDD. Accordingly, the precharge voltagecan be secured no generating a particular control signal.

The above-mentioned operation of the semiconductor memory device isdescribed on the assumption that the high-level data ‘1’ is read out.Hereinafter, an operation of the semiconductor memory device for read alow-level data ‘0’ is described below.

In case that the low-level data ‘0’ is read, a cell capacitor of aselected unit cell is discharged. Accordingly, a voltage level of thefirst bit line BL receiving the low-level data is not changed at theread step after the precharge step, i.e., t1. That is, the voltage levelof the first bit line BL keeps a voltage level of the ground voltageGND.

Meanwhile, since the first bit line bar /BL receives a reference signal,a voltage level of the first bit line bar /BL is increased by apredetermined voltage level. Herein, an amount of the voltage increaseof the first bit line bar /BL is determined by a charge quantitycorresponding to the reference signal, i.e., a charge quantity stored inthe reference capacitor TOP_RC.

Thereafter, the bit line sense amplifier 210 senses the voltagedifference between the first bit line BL and the first bit line bar /BLto amplify the voltage level of the first bit line BL to the groundvoltage GND and the voltage level of the first bit line bar /BL to thesource voltage VDD respectively, then, the bit line sense amplifier 210latches the amplified voltage levels. Herein, the voltage level of thefirst bit line BL included in the first cell array 300a is maintained asthe ground voltage GND by the first connection unit 250a.

Since the remaining operations for reading the low-level data ‘0’ issame to that for reading the high-level data ‘1’, detailed descriptionsare omitted.

Hereinafter, an operation of the semiconductor memory device for writingdata can be also described as shown in FIGS. 8 and 9.

The write operation is very similar to the read operation. While a datasignal sensed and amplified by the bit line sense amplifier 210 isoutputted to the local data bus line pair LDB and LDBB during t3, a datasignal inputted in response to a write command is transferred to the bitline sense amplifier 210 through the local data bus line pair LDB andLDBB at the write operation.

Then, the bit line sense amplifier 210 replaces a previously latcheddata signal with the delivered data signal, and the newly latched datasignal is stored to a unit cell at the restore step (t4). The bit linesense amplifier 210 also performs a sensing and amplifying operation byusing the source voltage VDD and the first negative low voltage VBB_H atthe write operation.

As the above mentioned, the semiconductor memory device floats each ofthe first bit line pair BL and /BL at the precharge step, and the bitline sense amplifier 210 senses and amplifies a voltage differencebetween the first bit line pair BL and /BL by using the source voltageVDD and the first negative low voltage VBB_H.

FIG. 10 is a layout showing the bit line sense amplifying block 200 ofthe semiconductor memory device shown in FIG. 8. FIG. 11 iscross-sectional view describing the layout of the bit line senseamplifying block 200 shown in FIG. 10.

Hereinafter, the layout of the semiconductor memory device can beimplemented as shown in FIGS. 10 and 11.

As shown, the semiconductor memory device in accordance with the presentinvention has a folded bit line structure and operates by receiving asource voltage VDD and a ground voltage GND.

Referring to FIG. 10, the semiconductor memory device includes a firstP-well PW_1, a second P-well PW_2 and, a second N-well NW_2.

The first P-well PW_1 includes a first cell array and a first prechargeNMOS transistor TP1. The first cell array stores data and outputs thedata to one of the first bit line BL and the first bit line bar /BLselected among the plurality of bit lines provided in the plurality ofunit cells. The first precharge NMOS transistor TP1 having an N-channelequalizes voltage levels of the first bit line pair BL and /BL in thefirst cell array during a precharge step.

The second N-well NW_2 includes first and second sense amplifying PMOStransistors TS1 and TS2, and first and second connection PMOStransistors TBH1 and TBH2. The first and the second sense amplifyingPMOS transistors TS1 and TS2 having a P-channel, among a plurality ofsense amplifying MOS transistors, senses and amplifies a signaldifference between the first bit line BL and the first bit line bar /BL.The first and the second connection PMOS transistors TBH1 and TBH2having a P-channel connects or disconnects the first bit line pair BLand /BL from/to the first and the second sense amplifying PMOStransistors TS1 and TS2.

The second P-well PW_2 includes first and second sense amplifying NMOStransistors TS3 and TS4 have an N-channel among the plurality of senseamplifying MOS transistors for sensing and amplifying the signaldifference between the first bit line pair BL and /BL.

In accordance with the preferred embodiment of the present invention,the semiconductor memory device floats the first bit line pair BL and/BL by not proving a special precharge voltage to the first bit linepair BL and /BL during the precharge step.

In addition, in the preferred embodiment of the present invention, thefirst and the second sense amplifying PMOS transistors TS1 and TS2having the P-channel perform a sensing and amplifying operation by usingthe low voltage VBB having the lower voltage level than the groundvoltage GND, and the first and the second sense amplifying NMOStransistors TS3 and TS4 having the N-channel perform a sensing andamplifying operation by using the source voltage VDD or a high voltageVPP having the higher voltage level than the source voltage VDD.

The first P-well PW_1 further includes first and second auxiliary MOStransistors TSB1 and TSB2 having an N-channel for sensing and amplifyinga lower voltage level of the first bit line pair BL and /BL, which islocated between the first cell array and the first and the secondconnection PMOS transistors TBH1 and TBH2, as the voltage level of theground voltage GND.

The semiconductor memory device in accordance with the present inventionfurther includes a third P-well PW_3. The third P-well PW_3 includes asecond cell array and a second precharge NMOS transistor TP2. The secondcell array stores data and outputs the data to one of the second bitline BOT_BL and the second bit line bar /BOT_BL selected among aplurality of bit lines provided in the plurality of unit cells. Thesecond precharge NMOS transistor TP2 having an N-channel equalizesvoltage levels of the second bit line pair BOT_BL and /BOT_BL in thesecond cell array during the precharge step.

The second N-well NW_2 further includes third and fourth connection PMOStransistors TBL1 and TBL2 having a P-channel for connecting ordisconnecting the second bit line pair BOT_BL and /BOT_BL to the firstand the second sense amplifying PMOS transistors TS1 and TS2, and thefirst and the second sense amplifying NMOS transistors TS3 and TS4.

As described above, the second N-well NW_2 includes the first to thefourth connection PMOS transistors TBH1, TBH2, TBL1 and TBL2, and thefirst and the second sense amplifying PMOS transistors TS1 and TS2. Thesecond P-well PW_2 includes the first and the second sense amplifyingNMOS transistors TS3 and TS4. Accordingly, the second P-well PW_2 iswrapped up in the second N-well NW_2 as shown in FIG. 11.

Hereinafter, the third P-well PW_3 further includes third and fourthauxiliary NMOS transistors TSB3 and TSB4 having an N-channel for sensingand amplifying a lower voltage level of the second bit line pair BOT_BLand /BOT_BL, which is located between the second cell array and thethird and the fourth connection PMOS transistors TBL1 and TBL2, as thevoltage level of the ground voltage GND.

In addition, the second P-well PW_2 further includes first and secondinput/output NMOS transistors T01 and T02 having an N-channel forconnecting the data sensed and amplified by the plural sense amplifyingMOS transistors TS1 to TS4 to a local data bus line pair LDB and LDBB.

Each of the first to the third P-well PW_1 to PW_3 and the second N-wellNW_2 is formed over a P-type substrate. The P-type substrate furtherincludes a first N-well NW_1 and a third N-well NW_3. Herein, the firstP-well PW_1 is wrapped up in the first N-well NW_1 and the third P-wellPW_3 is wrapped up in the third N-well NW_3 as shown in FIG. 11.

Meanwhile, each of the N-wells and the P-wells can be formed over theP-type substrate, opposite to each other. In this case, each MOStransistor included in the N-wells and the P-wells has an oppositepolarity channel.

As described above, the semiconductor memory device floats thecorresponding bit line pair during the precharge step and the bit linesense amplifier senses and amplifies the voltage difference between thebit line pair using the low voltage and the source voltage.

Since each of the first and the second connection unit includes pluralPMOS transistors, even though the bit line sense amplifier senses andamplifies the voltage difference using the low voltage and the sourcevoltage, the low voltage VBB is not transferred to the cell array. Atthe same time, the semiconductor memory device further includes thefirst and the second auxiliary bit line sense amplifier so that the bitline coupled to the cell array is not to be under the ground voltage.

As shown in FIG. 11, each of the first to the third N-wells NW_1 to NW_3is supplies with first to third positive voltage VP1, VP2 and VP3, andeach of the first to the third P-wells PW_1 to PW_3 is supplies withfirst to third negative voltage VN1, VN2 and VN3.

Generally, as an operating voltage of the semiconductor memory device issmaller, an operating margin of each threshold voltage of PMOS and NMOStransistors included in the semiconductor memory device is notsufficient; and, as a result, an operation reliability of the bit linesense amplifier is not guaranteed.

Herein, an absolute quantity of each threshold voltage of the PMOS andthe NMOS transistors is increased in proportion to a voltage levelsupplied to each of the N-wells and the P-wells. That is, in case of anNMOS transistor having an N-channel, as the absolute quantity of avoltage level of a negative voltage, i.e., VN1 to VN3, supplied to theP-well is increased, a threshold voltage of the NMOS transistor isincreased. Likewise, in case of a PMOS transistor having a P-channel, asthe absolute quantity of a voltage level of a positive voltage, i.e.,VP1 to VP3, supplied to the N-well is increased, a threshold voltage ofthe PMOS transistor is increased.

Accordingly, even though each of the NMOS and the PMOS transistor has asame size, each threshold voltage of the NMOS and the PMOS transistor isdifferent according to the voltage level supplied to each of the N-wellsand the P-wells. As a result, a current driving ability of each MOStransistor included in the corresponding well depends on a bulk voltagesupplied to each well. In addition, under a low supply voltagecondition, since the operating margin of each threshold voltage of PMOSand NMOS transistors included in the semiconductor memory device is notsufficient, a variation of the threshold voltage has influence on theoperation reliability.

In the semiconductor memory device, an operation reliability of the bitline sense amplifier has a great influence on a circuit driving ability.Specially, the bit line sense amplifier is sensitive to the low supplyvoltage because the bit line sense amplifier stars to amplify a sensedvoltage at the precharge voltage of the bit line pair, e.g., a half ofthe source voltage VDD.

In accordance with the present invention, each bulk voltage can besupplied to a corresponding well area by separating a well area forforming the bit line sense amplifier from a well area for forming thecell array.

When the cell array includes a plurality of unit cells having an NMOStransistor and a cell capacitor, it is important to arrange the PMOStransistor of the bit line sense amplifier, which operates by using anegative low voltage and connects the bit line sense amplifier to thecell array.

Accordingly, in accordance with the present invention referring to FIG.10, the semiconductor memory device largely defines three well areas tothereby supply an optimum bulk voltage to each well area: a first wellarea WELL_1 includes the first cell array and the first precharge unit220a; a second well area WELL_2 includes the bit line sense amplifier210 and the first and the second connection unit 250a and 250b; and athird well area WELL_3 includes the second cell array and the secondprecharge unit 220b.

In addition, the second well area WELL_2 further defines two well area,i.e., the second P-well PW_2 and the second N-well NW_2, to therebyarrange the first and the second sense amplifying PMOS transistors TS1and TS2 to the second N-well NW_2, and the first and the second senseamplifying NMOS transistors TS3 and TS4 to the second P-well PW_2. Atthe same time, the first to the fourth connection PMOS transistors TBH1,TBH2, TBL1 and TBL2 are formed at the second N-well NW_2 where the firstand the second sense amplifying PMOS transistors TS1 and TS2 is located.Accordingly, the second P-well PW_2 is wrapped up in the second N-wellNW_2 as shown in FIG. 11. Further, it is possible to effectively connectthe first and the second cell array with the bit line sense amplifier210 included in the first and the third well areas WELL_1 and WELL_3.

As described above, the PMOS and the NMOS transistors provided in thesemiconductor memory device can be effectively arranged so that theoptimum bulk voltage is supplied to the PMOS and the NMOS transistors tothereby get an optimum threshold voltage of each PMOS and each NMOStransistor.

Effective advantages of the semiconductor memory device in accordancewith the present invention are described below.

Firstly, since a particular precharge voltage is not needed to besupplied at a precharge step, a power consumption at the precharge stepcan be reduced. That is, according to the conventional invention, sincea source voltage or a half of a supply voltage VDD is provided for theprecharge step, a predetermined amount of power is consumed. However,since the semiconductor memory device in accordance with the presentinvention does not need an additional power for the precharge step, thepower consumption can be dramatically reduced.

Secondly, a bleed current caused by a short-circuit between a word lineand a bit line of a unit cell can be prevented. As above-mentioned,since the bleed current is still generated after the word line isreplaced with a redundancy word line, a power is unnecessarily consumed.However, in accordance with the present invention, there is noparticular precharge voltage for the bit line and the bit line isfloated. Therefore, the bit line has a voltage level of a ground voltageGND and, thus, the bleed current can be prevented because there is novoltage difference between the word line and the bit line. Herein, at aninitial state of the precharge step, since the bit line has apredetermined voltage level, a little bleed current may be generated;however, the bleed current is not generated after a voltage level of thefloated bit line becomes the ground voltage GND.

Thirdly, since a bit line sense amplifier performs a sensing andamplifying operation by using the source voltage VDD and a low voltageVBB which is lower than the ground voltage GND, a data signal deliveredto the bit line can sensed and amplified by the bit line sense amplifierat a high speed even though the source voltage VDD is low. Also, anabsolute quantity of the low voltage VBB may be same to that of thesource voltage VDD as an operational voltage of the semiconductor memorydevice is decreased. In this case, a half of the source voltage VDDbecomes the ground voltage GND. Accordingly, the bit line senseamplifier amplifies a high-level data to the source voltage VDD and alow-level data to the low voltage VBB and, then, at the precharge step,a voltage level of the bit line pair is maintained as the ground voltageGND.

Fourthly, according to the conventional invention, since the prechargevoltage level is a source voltage VDD or a half of the source voltageVDD, a current is flown from a data line to a bit line and, thus, avoltage level of a bit line amplified to a low level is temporarilyincreased. However, in accordance with the present invention, since thebit line sense amplifier amplifies a voltage level of a bit line to anegative low voltage, the current flown from the data line iscompensated by the negative low voltage. Therefore, a voltage level ofthe bit line is not increased more than the ground voltage. As a result,a period of the restore step can be decreased and a cycle time also canbe decreased.

Lastly, since the semiconductor memory device is operated by using a lowvoltage restraining using a high voltage, a power consumption forgenerating the high voltage can be reduced. That is, an absolutequantity of the low voltage is smaller than that of the high voltage andcharacteristics of the low voltage is better than that of the highvoltage.

As a result, in accordance with the present invention, the semiconductormemory device can perform a data access operation at a high speed undera low operational voltage. In addition, in case of a semiconductormemory device having a folded bit line structure with a shared bit linestructure, it is possible to get an optimum threshold voltage of eachPMOS and each NMOS transistor provided in the semiconductor memorydevice by forming each cell array and a bit line sense amplifier using aseparate well area.

The present application contains subject matter related to Korean patentapplication No. 2005-27382, filed in the Korean Patent Office on Mar.31, 2005, the entire contents of which being incorporated herein byreference.

While the present invention has been described with respect to theparticular embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

What is claimed is:
 1. A semiconductor memory device having a folded bitline structure and operating with a source voltage and a ground voltage,comprising: a first first-type well including a first cell array forproviding data to a first bit line or a first bit line bar selectedamong a plurality of bit lines, and a first precharge MOS transistorhaving a second-type channel for equalizing voltage levels of the firstbit line and the first bit line bar during a precharge period; a firstsecond-type well including a first sense amplifying MOS transistorhaving a first-type channel among a plurality of sense amplifying MOStransistors for sensing and amplifying a signal difference between thefirst bit line and the first bit line bar, and a first connection MOStransistor and a second connection MOS transistor having a first-typechannel for connecting or disconnecting the first bit line and the firstbit line bar to or from the first sense amplifying MOS transistor; and asecond first-type well including a second sense amplifying MOStransistor having a second-type channel among the plurality of senseamplifying MOS transistors for sensing and amplifying the signaldifference between the first bit line and the first bit line bar, eachof the first and second first-type wells being supplied with a differentbulk voltage.
 2. The semiconductor memory device as recited in claim 1,wherein the first bit line and the first bit line bar are floated duringthe precharge period.
 3. The semiconductor memory device as recited inclaim 2, wherein the second sense amplifying MOS transistor performs asensing and amplifying operation by using a low voltage lower than theground voltage.
 4. The semiconductor memory device as recited in claim3, wherein the first sense amplifying MOS transistor performs a sensingand amplifying operation by using a high voltage higher than the sourcevoltage.
 5. The semiconductor memory device as recited in claim 3,wherein the first sense amplifying MOS transistor performs a sensing andamplifying operation by using the source voltage.
 6. The semiconductormemory device as recited in claim 2, wherein the first first-type wellincludes a first auxiliary MOS transistor having a second-type channelfor sensing and amplifying a lower voltage level of the first bit lineand the first bit line bar, which are located between the first cellarray and the first and second connection MOS transistor transistors, asa voltage level of the ground voltage.
 7. The semiconductor memorydevice as recited in claim 6, further comprising a third first-type wellincluding a second cell array for storing data to be applied to one of asecond bit line and a second bit line bar selected among the pluralityof bit lines, and a second precharge MOS transistor having a second-typechannel for equalizing voltage levels of the second bit line and thesecond bit line bar during the precharge period.
 8. The semiconductormemory device as recited in claim 7, wherein the first second-type wellincludes a second third connection MOS transistor and a fourthconnection MOS transistor having a first-type channel for connecting ordisconnecting the second bit line and the second bit line bar to or fromthe first and the second sense amplifying MOS transistors.
 9. Thesemiconductor memory device as recited in claim 8, wherein the thirdfirst-type well includes a second auxiliary MOS transistor having asecond-type channel for sensing and amplifying a lower voltage level ofthe second bit line and the second bit line bar, which are locatedbetween the second cell array and the second third and fourth connectionMOS transistor transistors, as the voltage level of the ground voltage.10. The semiconductor memory device as recited in claim 9, wherein thesecond first-type well includes an input/output MOS transistor having asecond-type channel for connecting the data sensed and amplified by thefirst and the second sense amplifying MOS transistors to a local databus line.
 11. The semiconductor memory device as recited in claim 10,wherein the first to third first-type wells, and the first second-typewell are formed over a first-type substrate.
 12. The semiconductormemory device as recited in claim 11, wherein the first-type substrateincludes a second second-type well for wrapping up the first first-typewell and a third second-type well for wrapping up the third first-typewell.
 13. The semiconductor memory device as recited in claim 12,wherein each of the first to the third first-type wells, and the firstand the second second-type wells is supplied with a different bulkvoltage.
 14. The semiconductor memory device as recited in claim 12,wherein the first-type is a P-type and the second-type is an N-type. 15.The semiconductor memory device as recited in claim 12, wherein thefirst-type is an N-type and the second-type is a P-type.
 16. Asemiconductor memory device having a folded bit line structure andoperating with a source voltage and a ground voltage, comprising: afirst well including a first cell array for providing data to a firstbit line or a first bit line bar selected among a plurality of bitlines; a second well including a second cell array for providing data toa second bit line or a second bit line bar selected among the pluralityof bit lines; a third well including a first sense amplifying MOStransistor having a first-type channel among a plurality of senseamplifying MOS transistors provided in a bit line sense amplifier, afirst connection unit for connecting or disconnecting the first bit lineand the first bit line bar to or from the bit line sense amplifier, anda second connection unit for connecting or disconnecting the second bitline and the second bit line bar to or from the bit line senseamplifier; and a fourth well including a second sense amplifying MOStransistor having a second-type channel among the plurality of senseamplifying MOS transistors provided in the bit line sense amplifier, thethird and the fourth wells being supplied with a different bulk voltage.17. The semiconductor memory device as recited in claim 16, wherein thefirst well includes a first precharge unit for equalizing voltage levelsof the first bit line and the first bit line bar during a prechargeperiod.
 18. The semiconductor memory device as recited in claim 17,wherein the second well includes a second precharge unit for equalizingvoltage levels of the second bit line and the second bit line bar duringthe precharge period.
 19. The semiconductor memory device as recited inclaim 18, wherein the first and the second precharge units float thefirst and the second bit lines and the first and the second bit linebars during the precharge period.
 20. The semiconductor memory device asrecited in claim 19, wherein the second sense amplifying MOS transistorperforms a sensing and amplifying operation by using a low voltage lowerthan the ground voltage.
 21. The semiconductor memory device as recitedin claim 19, wherein the first sense amplifying MOS transistor performsa sensing and amplifying operation by using a high voltage higher thanthe source voltage.
 22. The semiconductor memory device as recited inclaim 19, wherein the first sense amplifying MOS transistor performs asensing and amplifying operation by using the source voltage.
 23. Thesemiconductor memory device as recited in claim 19, wherein the firstwell includes a first auxiliary unit for sensing and amplifying a lowervoltage level of the first bit line and the first bit line bar, whichare located between the first cell array and the first connection unit,as a voltage level of the ground voltage.
 24. The semiconductor memorydevice as recited in claim 19, wherein the second well includes a secondauxiliary unit for sensing and amplifying a lower voltage level of thesecond bit line and the second bit line bar, which are located betweenthe second cell array and the second connection unit, as a voltage levelof the ground voltage.
 25. The semiconductor memory device as recited inclaim 19, wherein the fourth well includes a data input/output unit foroutputting data sensed and amplified by the bit line sense amplifierthrough a local data bus line to an external circuit, or for deliveringdata inputted from the external circuit via the local data bus line tothe bit line sense amplifier.
 26. The semiconductor memory device asrecited in claim 19, wherein the first to the fourth wells are formedover a first-type substrate.
 27. The semiconductor memory device asrecited in claim 26, wherein the fourth well is wrapped up in the thirdwell.
 28. The semiconductor memory device as recited in claim 26,wherein each of the first to the fourth wells is supplied with adifferent bulk voltage.
 29. The semiconductor memory device as recitedin claim 26, wherein the first-type is a P-type and the second-type isan N-type.
 30. The semiconductor memory device as recited in claim 26,wherein the first-type is an N-type and the second-type is a P-type. 31.The semiconductor memory device as recited in claim 16, wherein: thefirst connection unit comprises: a first MOS transistor connected inseries between the first bit line and a first input of the bit linesense amplifier; and a second MOS transistor connected in series betweenthe first bit line bar and a second input of the bit line senseamplifier; and the second connection unit comprises: a first MOStransistor connected in series between the second bit line and a firstinput of the bit line sense amplifier; and a second MOS transistorconnected in series between the second bit line bar and a second inputof the bit line sense amplifier.
 32. The semiconductor memory device asrecited in claim 31, wherein: the first and second MOS transistors ofthe first connection unit are PMOS transistors; and the first and secondMOS transistors of the second connection unit are PMOS transistors. 33.The semiconductor memory device as recited in claim 16, wherein: thefourth well is wrapped up in the third well.
 34. The semiconductormemory device as recited in claim 16, wherein: the first and the secondwells are supplied with a bulk voltage different from the bulk voltagesof the third and the fourth wells.
 35. A semiconductor memory devicehaving a folded bit line structure and operating with a source voltageand a ground voltage, comprising: a first first-type well including afirst cell array for providing data to a first bit line or a first bitline bar selected among a plurality of bit lines, and a first prechargeMOS transistor having a second-type channel for equalizing voltagelevels of the first bit line and the first bit line bar during aprecharge period; a first second-type well including a first senseamplifying MOS transistor having a first-type channel among a pluralityof sense amplifying MOS transistors for sensing and amplifying a signaldifference between the first bit line and the first bit line bar, and afirst connection MOS transistor and a second connection MOS transistorhaving a first-type channel for connecting or disconnecting the firstbit line and the first bit line bar to or from the first senseamplifying MOS transistor; and a second first-type well including asecond sense amplifying MOS transistor having a second-type channelamong the plurality of sense amplifying MOS transistors for sensing andamplifying the signal difference between the first bit line and thefirst bit line bar, the first second-type well being supplied with avariable bulk voltage to vary a threshold voltage of the first andsecond connection MOS transistors.
 36. A semiconductor memory devicehaving a folded bit line structure and operating with a source voltageand a ground voltage, comprising: a first well including a first cellarray for providing data to a first bit line or a first bit line barselected among a plurality of bit lines; a second well including asecond cell array for providing data to a second bit line or a secondbit line bar selected among the plurality of bit lines; a third wellincluding a first sense amplifying MOS transistor having a first-typechannel among a plurality of sense amplifying MOS transistors providedin a bit line sense amplifier, a first connection unit for connecting ordisconnecting the first bit line and the first bit line bar to or fromthe bit line sense amplifier, and a second connection unit forconnecting or disconnecting the second bit line and the second bit linebar to or from the bit line sense amplifier; and a fourth well includinga second sense amplifying MOS transistor having a second-type channelamong the plurality of sense amplifying MOS transistors provided in thebit line sense amplifier, the third well being supplied with a variablebulk voltage to vary a threshold voltage of the first and secondconnection units.